The present invention claims the benefit of Korean Patent Application No. 2001-87619, filed in Korea on Dec. 28, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an In-Plane Switching (IPS) mode liquid crystal display device and fabricating method for the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices commonly make use of optical anisotropy and polarization properties of liquid crystal molecules to produce image data. The liquid crystal molecules have a definite alignment direction resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by application of an electric field. Accordingly, as the alignment direction of the applied electric field is changed, the alignment of the liquid crystal molecules also changes. Because incident light is refracted by the orientation of the liquid crystal molecules due to their optical anisotropy, image data is displayed. Active matrix liquid crystal display (LCD) devices, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are commonly used because of their high resolution and superiority in displaying moving images. An array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device and a fabrication method for the same will be described hereinafter with reference to figures attached.
FIG. 1 is a plan view of a pixel of an array substrate for a related art in-plane switching (IPS) mode liquid crystal display (LCD) device. In FIG. 1, the array substrate for the in-plane switching (IPS) mode liquid crystal display (LCD) device has a plurality of gate lines 12, common lines 16 and data lines 24, wherein the gate line 12 and the common line 16 are formed along a horizontal direction and the data line 24 crosses the gate line 12 and the common line 16, thereby defining a pixel region xe2x80x9cPxe2x80x9d by crossing the data line 24. A gate pad electrode 13 is formed at one end of the gate line 12, and a data pad electrode 25 is formed at one end of the data line 24. A thin film transistor xe2x80x9cTxe2x80x9d is formed at a cross point of the gate and data lines 12 and 24. The thin film transistor xe2x80x9cTxe2x80x9d includes a gate electrode 14, an active layer 20, a source electrode 26, and a drain electrode 28. The gate electrode 14 extends from the gate line 12, and the source electrode 26 is electrically connected to the data line 24. A pixel electrode 30 and a common electrode 17 are formed within the pixel region xe2x80x9cP,xe2x80x9d wherein the pixel electrode 30 is electrically connected to the drain electrode 28. The common electrode 17 is formed parallel with the pixel electrode 30 and is electrically connected to the common line 16. The pixel electrode 30 includes an extension portion 30a, a plurality of vertical portions 30b, and a horizontal portion 30c. The extension portion 30a extends from the drain electrode 28, the vertical portion 30b vertically extends from the extension portion 30a, and the extension and vertical portions 30a and 30b are spaced apart from each other. The horizontal portion 30c is disposed over the common line 16, and electrically interconnects the plurality of vertical portions 30b. The common electrode 17 has a plurality of vertical portions 17b and a horizontal portion 17a. The vertical portions 17b vertically extend from the common line 16 and are arranged in an alternating pattern with the vertical portion 30b of the pixel electrode 30. The horizontal portion 17a electrically interconnects the plurality of vertical portions 17b. The vertical portion 17b is spaced apart from the data line 24. A storage capacitor xe2x80x9cCxe2x80x9d is formed within the pixel region xe2x80x9cP,xe2x80x9d and uses a portion of the common line 16 as a first storage electrode and a horizontal portion 30c of the pixel electrode 30 as a second electrode. The gate pad electrode 13 electrically contacts a gate pad terminal electrode 30 through a gate pad contact hole 33. The data pad electrode 25 electrically contacts a data pad terminal electrode 41 through a data pad contact hole 35. The source electrode 25, the drain electrode 28, and the data line 24 are formed to have a single layer using one of molybdenum (Mo) or chromium (Cr). However, metals such as molybdenum (Mo) or chromium (Cr), which are used for the source and drain electrode 26 and 28, have a high electric resistance and are not suitable for large-sized liquid crystal display panels.
FIGS. 2A to 2D are cross-sectional views taken along IIxe2x80x94II, IIIxe2x80x94III, IVxe2x80x94IV and Vxe2x80x94V of FIG. 1 and illustrate a fabrication sequence of an array substrate according to the related art. In FIG. 2A, the gate line 12, the gate pad electrode 13, and the common line 16 are formed on the substrate 10 by depositing and patterning a conductive metal material, such as aluminum (Al) and an aluminum alloy. The gate electrode 14 is a part of the gate line 12, and the common line 16 is spaced apart from the gate line 12. The plurality of vertical portions 17b of the common electrode 17 vertically extend from the common line 16, and the horizontal portion 17a (not shown) of the common electrode 17 electrically interconnects the plurality of vertical portions 17b. The gate electrode 14, the gate line 12, and the gate pad electrode 13 have a dual-layer structure. The dual-layer structure of the gate line 12 and the gate electrode 14 includes aluminum (Al). For example, aluminum (Al) is used for a first metal layer and molybdenum (Mo) or chromium (Cr) is used for a second metal layer. Then, a gate insulating layer 18 is formed on the substrate 10 using silicon nitride (SiNx). A first pattern 20, a second pattern 21, and a third pattern 22 are formed by simultaneously depositing and patterning amorphous silicon (a-Si:H) and impurities doped amorphous silicon (n+a-Si:H) on the gate insulating layer 18. The first pattern 20 is disposed within an active region xe2x80x9cAxe2x80x9d over the gate electrode 14, the second pattern 21 over the common line 16 and the third pattern within a data pad region xe2x80x9cD.xe2x80x9d The second pattern 21 and the third pattern 22 improve a contact property of a metal layer that will be formed thereon in a later process. An amorphous silicon (a-Si:H) layer of the first pattern 20 is commonly referred to as an active layer 20a, and an impurities doped amorphous silicon (n+a-Si:H or p+a-Si:H) of the first pattern 20 is commonly referred to as an ohmic contact layer 20b. 
In FIG. 2B, the data line 24, the source electrode 26, the drain electrode 28, and the pixel electrode 30b and 30c are formed by depositing and patterning one of chromium (Cr) and molybdenum (Mo) on the substrate 10. The data line 24 defines the pixel region xe2x80x9cPxe2x80x9d by crossing the gate line 12. The source electrode 26 extends from the data line 24 and electrically contacts the ohmic contact layer 20b, and the drain electrode 28 is spaced apart from the source electrode 26. The pixel electrode 30 includes the extension portion 30a (not shown), the plurality of vertical portions 30b, and the horizontal portion 30c. The data pad electrode 25 is formed at one end of the data line 24.
In FIG. 2C, a passivation layer 32 is formed by depositing silicon nitride (SiNx) on the substrate 10. A gate pad contact hole 33 is formed to expose a portion of the gate pad electrode 13, and a data pad contact hole 35 is formed to expose a portion of the data pad electrode 25 by patterning the passivation layer 32.
In FIG. 2D, both the gate pad terminal electrode 39 is formed with the gate pad electrode 13 and the data pad terminal electrode 41 is formed with the data pad electrode 25 by depositing and patterning transparent conductive metal material, such as indium tin oxide (ITO) on the substrate 10. The storage capacitor xe2x80x9cCxe2x80x9d is formed between the common line 16 and the horizontal portion 30c of the pixel electrode 30. The storage capacitor xe2x80x9cCxe2x80x9d uses the portion of the common line 16 as the first storage electrode and the horizontal portion 30c of the pixel electrode 30 as the second storage electrode. The gate insulating layer 18 and the second pattern 21 are disposed between the common line 16 and the horizontal portion 30c of the pixel electrode 30.
Accordingly, the present invention is directed to an array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device and fabrication method for the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device in which a metal layer of a source electrode, a drain electrode, and a data line has a dual-layer structure for manufacturing a large size liquid crystal display panel.
Another object of the present invention is to provide a fabrication method of an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device in which a metal layer of a source electrode, a drain electrode, and a data line has a dual-layer structure for manufacturing a large size liquid crystal display panel.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device including a substrate, a plurality of gate lines disposed along a first direction on the substrate, a plurality of data lines disposed along a second direction perpendicular to the first direction on the substrate to define a plurality of pixel regions, a pixel electrode and a common electrode on the substrate, the pixel electrode including an extension portion, a plurality of vertical portions, and a horizontal portion, and a transparent electrode contacting the horizontal portion of the pixel electrode and extending over one of the gate lines, wherein the data line includes aluminum dual layer structure having a first metal layer and a second metal layer.
In another aspect, an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device includes a substrate, a plurality of gate lines, a plurality of common lines, and a gate pad electrode on the substrate, the gate pad electrode extending from the gate lines, a plurality of data lines and a data pad electrode extending from the data lines, source and drain electrodes on the substrate, a pixel electrode and a common electrode on the substrate, the pixel electrode including an extension portion, a plurality of vertical portions, and a horizontal portion, and a transparent electrode, a gate pad terminal electrode, and a data pad terminal electrode, the transparent electrode contacting the pixel electrode and extending over the gate line, the gate pad terminal electrode contacting the gate pad electrode, and the data pad terminal electrode contacting the data pad electrode, wherein the data lines, the data pad, and the source and drain electrodes include an aluminum dual-layer structure having a first metal layer and a second metal layer.
In another aspect, a method for fabricating an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device includes forming a plurality of gate lines on a substrate, forming a plurality of data lines crossing the gate lines, the data lines including an aluminum dual-layer structure having a first metal layer and a second metal layer, forming a pixel electrode and a common electrode on the substrate, the pixel electrode having an extension portion, a plurality of vertical portions, and a horizontal portion, and forming a transparent electrode contacting the horizontal portion of the pixel electrode and extending over the gate lines.
In another aspect, a method for fabricating an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device includes forming a plurality of gate lines, a plurality of common lines, and a gate pad electrode on a substrate, the gate pad electrode extending from the gate lines, forming a plurality of data lines and a data pad electrode, the data lines and the data pad electrode including an aluminum dual-layer structure having a first metal layer and a second metal layer, the data pad electrode extending from the data line, forming a pixel electrode and a common electrode on the substrate, the pixel electrode having an extension portion, a plurality of vertical portions, and a horizontal portion, and forming a transparent electrode, a gate pad terminal electrode, and a data pad terminal electrode, wherein the transparent electrode contacts the horizontal portion of the pixel electrode and extends over the gate lines, the gate pad terminal electrode contacts the gate pad electrode, and the data pad terminal electrode contacts the data pad electrode.
In another aspect, a method for fabricating an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device includes forming a plurality of gate lines, a plurality of common lines, and a gate pad electrode on a substrate, the gate pad electrode extending from the gate lines, forming a plurality of data lines and a data pad electrode on the substrate, the data lines and the data pad electrode including an aluminum dual-layer structure having a first metal layer and a second metal layer, and the data pad electrode extending from the data line, forming source and drain electrodes on the substrate, the source and drain electrodes including an aluminum dual-layer structure having a first metal layer and a second metal layer, forming a pixel electrode and a common electrode on the substrate, the pixel electrode having an extension portion, a plurality of vertical portions, and a horizontal portion, and forming a transparent electrode, a gate pad terminal electrode, and a data pad terminal electrode, wherein the transparent electrode contacts the horizontal portion of the pixel electrode and extends over the gate lines, the gate pad terminal electrode contacts the gate pad electrode, and the data pad terminal electrode contacts the data pad electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.